The present invention relates to a data processor and, more particularly, to a processor in which a program memory for storing a string of instructions and an execution unit for decoding and executing each instruction are provided in a single semiconductor chip.
In a data processor fabricated on a single semiconductor chip such as a single-chip microcomputer or a single-chip peripheral controller for a disk drive, a display unit, etc., the operable functions thereof are determined by instructions stored in a program memory provided in the processor. That is, the processing capability is restricted by the number of and the bit length of instructions which are stored in the program memory, or by the capacity of the program memory. If the number of instructions and/or the bit length of each instruction is increased for expanding the processing capability, a structural design change is required wherein the memory capacity of the program memory and the bit length of a program counter must be enlarged. For this reason, even when a version-up processor is developed in which new operating functions are added to the previously developed processor or in which a part of the functions of the previously developed processor is improved, a new design of such a version-up processor requires a long time of duration. Moreover, the addition of new instructions increases the number of reading-out and decoding operations, so the processing speed is lowered.